The present invention relates to a solid-state image sensing device and, more particularly, to a solid-state image sensing device in which a charge removing portion for removing excess charges is formed adjacent to a horizontal charge transfer portion.
A solid-state image sensing device conventionally used as an input device for a camera-integrated VTR (Video Tape Recorder) is being used as an input device for an electronic still camera used to convert optical information into an electrical signal, store it in a storage medium, and form a hard copy of this optical information or enjoy it on a monitor screen, instead of exposing a film.
A solid-state image sensing device of this type has a photoelectric conversion portion, and charge transfer portions for vertically and horizontally transferring signal charges accumulated at this photoelectric conversion portion. With these portions, the solid-state image sensing device can output optical information as an electrical signal. In the solid-state image sensing device, unwanted signal charges such as charges photoelectrically converted in an unwanted period and charges generated at the interface of silicon and silicon oxide films exist in addition to signal charges of originally necessary video signals. When the solid-state image sensing device is used as the input device for the camera-integrated VTR, no unwanted signal charge poses any problem because it settles at a level free from any problem after displaying several frames.
When, however, the solid-state image sensing device is used as the input device for the electronic still camera, unwanted signal charges are superposed on signal charges of original video signals to degrade the image quality. If removal of unwanted signal charges takes a long time, a time lag is generated between triggering by the shutter button and actual opening/closing of the shutter, and the shutter chance may be lost.
For this reason, in the solid-state image sensing device used as the input device for the electronic still camera, unlike the one used in the camera-integrated VTR, all unwanted signal charges present at the photoelectric conversion portion and the vertical and horizontal charge transfer portions must be instantaneously removed at the same time the shutter button is triggered.
As a means of removing unwanted charges, removal of unwanted charges present at the photoelectric conversion portion employs a vertical overflow drain structure in which a lightly doped, thin p.sup.- -type semiconductor region is formed immediately below an n-type semiconductor region constituting the photoelectric conversion portion, and a reverse bias voltage is applied to an n-type semiconductor device therebelow to deplete the n-type semiconductor region itself and remove all signal charges to the n-type semiconductor substrate (see "CCD Image Sensor with Vertical Overflow Structure", Journal of the Japan TV Society, Vol. 37, No. 10, pp. 782-787, 1983).
Unwanted charges present at the horizontal charge transfer portion are removed to a reset drain formed at the end of the horizontal charge transfer portion by a normal operation because the horizontal transfer portion can operate at a high speed.
To remove unwanted charges present at the vertical charge transfer portion, transfer of at least one to several frames is required because the charge transfer ability of the horizontal charge transfer portion is limited. As a method of removing unwanted charges at the vertical charge transfer portion within a short time, an unwanted charge removing portion is formed adjacent to the horizontal charge transfer portion, and unwanted charges at the vertical charge transfer portion are transferred in the forward direction to the unwanted charge removing portion via the horizontal charge transfer portion (see Japanese Patent Laid-Open Nos. 62-154881 and 2-205359). By adopting this method, unwanted charges can be removed from the device within a short time together with the vertical overflow drain and high-speed transfer of the horizontal charge transfer portion, and an operative state as the input device for the electronic still camera can be formed immediately.
FIG. 19 shows the schematic arrangement of a solid-state image sensing device in which a charge removing portion is formed adjacent to a conventional horizontal charge transfer portion. In FIG. 19, the solid-state image sensing device is constituted by photoelectric conversion portions 11, vertical charge transfer portions 12, a horizontal charge transfer portion 13, an output circuit portion 14, a potential barrier portion 15, an unwanted charge removing portion 16, and an unwanted charge absorbing portion 17 formed at one end of the unwanted charge removing portion 16 to be connected to a power supply voltage.
FIG. 20 shows a region X surrounded by the dotted line in FIG. 19. The conventional solid-state image sensing device having this structure is constituted to separately optimize the diffusion layers of the charge transfer portions 12 and 13 while giving importance to ensuring of the maximum charge handling amount for the vertical charge transfer portion 12 and the transfer efficiency in high-speed transfer for the horizontal charge transfer portion 13 (see IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, VOL. 37, pp. 222-223, FEBRUARY, 1994).
As shown in FIG. 20, a conventional solid-state image sensing device of this type comprises a vertical charge transfer channel 21, a horizontal charge transfer channel 22 having a charge accumulating region 23 and a charge barrier region 24, a potential barrier portion 25, an unwanted charge removing portion 26, a first horizontal charge transfer electrode 27 made of a first polysilicon layer, a second horizontal charge transfer electrode 28 made of a second polysilicon layer, and a final vertical charge transfer electrode 29.
FIGS. 21A and 21B respectively show a section taken along the line A-A' in FIGS. 19 and 20 and the potential. As shown in FIGS. 21A and 21B, a first p-type well layer 32 constituting the vertical charge transfer portion 12 and having an impurity concentration of about 1.0.times.10.sup.16 cm.sup.-3, and a second p-type well layer 33 constituting the horizontal charge transfer portion 13, the potential barrier portion 15, and the unwanted charge removing portion 16 and having an impurity concentration of about 2.5.times.10.sup.15 cm.sup.-3 are formed on an n.sup.-- -type semiconductor substrate 31 having an impurity concentration of about 2.5.times.10.sup.14 cm.sup.-3.
A first n-type semiconductor region 34 constituting a buried channel of the vertical charge transfer portion 12 and having an impurity concentration of about 2.5.times.10.sup.17 cm.sup.-3, a second n-type semiconductor region 35 constituting buried channels of the horizontal charge transfer portion 13 and the potential barrier portion 15 and having an impurity concentration of about 1.0.times.10.sup.17 cm.sup.-3 and an n.sup.+ -type semiconductor region 38 constituting the unwanted charge removing portion 16 and having an impurity concentration of about 5.0.times.10.sup.18 cm.sup.-3 are formed on the first and second p-type well layers 32 and 33.
A p.sup.+ -type semiconductor region 40 constituting an element isolation portion so as to surround an active region and having an impurity concentration of about 1.0.times.10.sup.18 cm.sup.-3 is formed on the second p-type well layer 33. The first horizontal charge transfer electrode 27 made of a first polysilicon layer 41 and the final vertical charge transfer electrode 29 made of a second polysilicon layer 42 are further formed on the substrate. The transfer electrodes 27 and 29 are surrounded by an insulating film 43. Reference numeral 18 denotes a vertical/horizontal connecting portion; and 19, a bus line wiring formation region.
A constant voltage V.sub.D is applied to the n.sup.+ -type semiconductor region 38 constituting the unwanted charge removing portion 16 via an n.sup.++ -type semiconductor region 39 (see FIG. 23A) constituting the unwanted charge absorbing portion 17 and having an impurity concentration of about 1.0.times.10.sup.20 cm.sup.-3. The potential barrier of the potential barrier portion 15 is formed utilizing the narrow channel effect.
FIGS. 22A and 22B respectively show a section taken along the line B-B' in FIG. 19 and the potential. In FIGS. 22A and 22B, the second p-type well layer 33 constituting the horizontal charge transfer portion 13 is formed on the n.sup.-- -type semiconductor substrate 31. The second n-type semiconductor region 35 constituting the buried channel of the horizontal charge transfer portion 13, an n.sup.- -type semiconductor region 37 having an impurity concentration of about 7.5.times.10.sup.16 cm.sup.-3, the n.sup.++ -type semiconductor region 39 constituting a floating diffusion layer portion and a reset drain portion, and the p.sup.+ -type semiconductor region 40 constituting the element isolation portion are formed on the second p-type well layer 33.
The second p-type well layer 33 also serves as a punch-through preventing layer for preventing punch-through from the floating diffusion layer portion and the reset drain portion as the n.sup.++ -type semiconductor region 39 to the n.sup.-- -type semiconductor substrate 31. The horizontal charge transfer electrodes (first and second horizontal charge transfer electrodes 27 and 28) made of the first and second polysilicon layers 41 and 42, an output gate, and the gate of a reset transistor are further formed on the substrate. The constant voltage V.sub.D is applied to the n.sup.++ -type semiconductor region 39 constituting the reset drain of signal charges.
FIGS. 23A and 23B respectively show a section taken along the line C-C' in FIG. 19 and the potential. In FIGS. 23A and 23B, the second p-type well layer 33 constituting the unwanted charge removing portion 16 is formed on the n.sup.-- -type semiconductor substrate 31. The n.sup.+ -type semiconductor region 38 constituting the unwanted charge removing portion 16, the n.sup.++ -type semiconductor region 39 constituting the unwanted charge absorbing portion 17, and the p.sup.+ -type semiconductor region 40 constituting the element isolation portion are formed on the second p-type well layer 33.
The second p-type well layer 33 also serves as a punch-through preventing layer for preventing punch-through from the n.sup.++ -type semiconductor region 39 formed as the drain portion at one end of the unwanted charge removing portion 16 to the n.sup.-- -type semiconductor substrate 31. The first polysilicon layer 41 (first horizontal charge transfer electrode 27) and the second polysilicon layer 42 (second horizontal charge transfer electrode 28) are formed on the substrate via the insulating film 43. The constant voltage V.sub.D is applied to the n.sup.+ -type semiconductor region 38 constituting the unwanted charge removing portion 16 via the n.sup.++ -type semiconductor region 39.
The operation of the conventional solid-state image sensing device having this structure will be described below. First of all, unwanted charges present at the photoelectric conversion portion 11 are removed. For this purpose, a lightly doped p.sup.- -type semiconductor region (not shown) is formed immediately below an n-type semiconductor region (not shown) constituting the photoelectric conversion portion 11. A high reverse bias voltage of normally about 25 V is applied to the n.sup.-- -type semiconductor substrate 31 to deplete the n-type semiconductor region itself and remove all signal charges to the n.sup.-- -type semiconductor substrate 31.
At the same time as this operation, unwanted charges present at the vertical charge transfer portion 12 are simultaneously transferred to the horizontal charge transfer portion 13 by, e.g., a four-phase clock pulse. At this time, a high-level voltage V.sub.H and a low-level voltage V.sub.L are respectively applied to .phi.H.sub.1 and .phi.H.sub.2 of the horizontal charge transfer electrodes 27 and 28, as shown in FIG. 24. Excess charges which cannot be accumulated at the horizontal charge transfer portion 13 are swept via a potential .psi.B of the potential barrier portion 15 to the n.sup.+ -type semiconductor region 38 of the unwanted charge removing portion 16 formed adjacent to the potential barrier portion 15, and absorbed and removed via the n.sup.++ -type semiconductor region 39.
The potential .psi.B of the potential barrier portion 15 is set deeper than a potential .psi.V.sub.H formed at the vertical/horizontal connecting portion 18 so as to prevent charges transferred to the horizontal charge transfer portion 13 from returning to the vertical charge transfer portion 12.
Unwanted charges left at the horizontal charge transfer portion 13 are absorbed in the n.sup.++ -type semiconductor region 39 of the reset drain formed at the end of the horizontal charge transfer portion 13 by a normal high-speed operation of the horizontal charge transfer portion 13 in response to a two-phase clock pulse shown in FIG. 24.
Subsequently, signal charges accumulated in the photoelectric conversion portion 11 by the light amount incident for a predetermined time are read to a corresponding vertical charge transfer portion 12, and vertically transferred to the horizontal charge transfer portion 13 via each vertical charge transfer portion 12. The signal charges are sent to the horizontal charge transfer portion 13 in units of horizontal lines, and horizontally transferred via the horizontal charge transfer portion 13 to be output via the output circuit portion 14.
In the fine solid-state image sensing device having a large number of pixels, the impurity concentrations of the p-type well layer and the n-type semiconductor region at the transfer portions 12 and 13 must be optimally set in order to allow the vertical charge transfer portion 12 to ensure a sufficient charge transfer amount and enable a high-speed transfer operation at the horizontal charge transfer portion 13. At the unwanted charge removing portion 16, the n.sup.+ -type semiconductor region 38 constituting the unwanted charge removing portion 16 must be kept in an undepleted state in order to allow rapid removal of unwanted charges. In the conventional solid-state image sensing device described above, since the respective regions are formed in separate diffusion steps to meet these demands, five impurity doping steps are required to form, e.g., the device shown in FIG. 21A. For this reason, in the conventional solid-state image sensing device capable of rapid removal of unwanted charges, the number of manufacturing steps is large, resulting in high product cost.
The n.sup.+ -type semiconductor region 38 constituting the unwanted charge removing portion 16 having a relatively high impurity concentration is formed adjacent to the horizontal charge transfer portion 13 below the horizontal charge transfer electrodes 27 and 28. For this reason, in forming a gate insulating film below the horizontal charge transfer electrodes 27 and 28 in the subsequent step, an abnormal diffusion layer is undesirably formed in the n-type semiconductor region serving as the channel region of the horizontal charge transfer portion 13 or the potential barrier portion 15 due to outward diffusion of an impurity from the n.sup.+ -type semiconductor region, varying the potential.